Methods applying a non-zero voltage differential across a memory cell not involved in an access operation

ABSTRACT

Methods applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data retention characteristics.

RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.13/403,109, titled “APPARATUS AND METHODS FOR APPLYING A NON-ZEROVOLTAGE DIFFERENTIAL ACROSS A MEMORY CELL NOT INVOLVED IN AN ACCESSOPERATION,” filed Feb. 23, 2012 (allowed), which is commonly assignedand incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to memory and, in particular,in one or more embodiments, the present disclosure relates to methodsfor applying a non-zero voltage differential across a memory cell notinvolved in an access operation and apparatus configured to perform suchmethods.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuit devices in computers or other electronic devices.There are many different types of memory including random-access memory(RAM), read only memory (ROM), dynamic random access memory (DRAM),synchronous dynamic random access memory (SDRAM), and flash memory.

Flash memory devices have developed into a popular source ofnon-volatile memory for a wide range of electronic applications. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Changes in threshold voltage of the memory cells, through programming(which is often referred to as writing) of data-storage structures,using charge-storage structures (e.g., floating gates or charge traps)or other physical phenomena (e.g., phase change or polarization),determine the data state of each cell. Common uses for flash memoryinclude personal computers, personal digital assistants (PDAs), digitalcameras, digital media players, cellular telephones, solid state drivesand removable memory modules, and the uses are growing.

There is a continuing desire to increase memory density, e.g., thenumber of bits of data that can be stored for a given integrated circuitdie area. However, as memory density increases, issues with dataretention tend to worsen.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternative methods for facilitating improvements in data retention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a memory device in communicationwith a processor as part of an electronic system, according to anembodiment.

FIGS. 2A-2B are schematics of portions of arrays of memory cells ascould be used in a memory device of the type described with reference toFIG. 1.

FIG. 3 is a graphical representation of threshold voltage ranges in anexample population of memory cells.

FIG. 4 is a chart showing one example of a plot of maximum absolutevalues for voltages across the gate dielectric that a memory cell mightexperience across the continuum of threshold voltages representingpossible data states of the memory cell.

FIG. 5 is a flowchart of a method of operating a memory device inaccordance with an embodiment.

FIG. 6 is a flowchart of a method of operating an electronic system inaccordance with an embodiment.

FIG. 7 is a schematic of a portion of an array of memory cells showingcombinatorial logic for use with embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown, byway of illustration, specific embodiments. In the drawings, likereference numerals describe substantially similar components throughoutthe several views. Other embodiments may be utilized and structural,logical and electrical changes may be made without departing from thescope of the present disclosure. The following detailed description is,therefore, not to be taken in a limiting sense.

As memory cells are scaled down, neutral Vt tends to decrease due toshort channel effects. Data retention characteristics can become worseif threshold voltages used to define data states are not altered toplace the neutral Vt toward the median of those threshold voltages.However, driving threshold voltage ranges more negative may not befeasible.

To facilitate improved data retention characteristics of memory cells,various embodiments seek to reduce the average electric field acrossgate dielectrics of a group of memory cells during a standby state,i.e., while those memory cells are not currently involved in an accessoperation. As used herein, involvement in an access operation means thatthe memory cell would receive an applied bias to one or more of itsnodes (e.g., control gate, body, source and/or drain) as part of theoperation to access (e.g., read, program or erase) one or more memorycells. For example, during a read operation addressed to one or moreselected memory cells of a block of memory cells of a NAND memory array,all memory cells of the block of memory cells may be involved in theread operation as typically all memory cells coupled to the same accessline of the one or more selected memory cells receive a read voltageapplied to their control gates, and all remaining memory cells of theblock of memory cells would typically receive a pass voltage applied totheir control gates to act as pass transistors while the selected memorycells are being sensed. Thus, memory cells involved in an accessoperation includes both memory cells selected for the access operationand memory cells that would receive an applied bias to facilitate theaccess operation on the selected memory cells.

FIG. 1 is a simplified block diagram of a first apparatus in the form ofa memory device 100 in communication with a second apparatus, in theform of a processor 130, and a third apparatus, in the form of a powersupply 140, as part of a fourth apparatus, in the form of an electronicsystem, according to an embodiment. Some examples of electronic systemsinclude computer servers, network devices, personal computers, personaldigital assistants (PDAs), digital cameras, digital media players,digital recorders, games, appliances, vehicles, wireless devices,cellular telephones and the like. The processor 130 may be a memorycontroller or other external host device.

Memory device 100 includes an array of memory cells 104 logicallyarranged in rows and columns. Memory cells of a logical row aretypically coupled to the same access line (commonly referred to as aword line) while memory cells of a logical column are typicallyselectively coupled to the same data line (commonly referred to as a bitline). A single access line may be associated with more than one logicalrow of memory cells and a single data line may be associated with morethan one logical column. Memory cells (not shown in FIG. 1) of at leasta portion of array of memory cells 104 are capable of being programmedto one of at least two data states.

A row decode circuitry 108 and a column decode circuitry 110 areprovided to decode address signals. Address signals are received anddecoded to access the array of memory cells 104. Memory device 100 alsoincludes input/output (I/O) control circuitry 112 to manage input ofcommands, addresses and data to the memory device 100 as well as outputof data and status information from the memory device 100. An addressregister 114 is in communication with I/O control circuitry 112 and rowdecode circuitry 108 and column decode circuitry 110 to latch theaddress signals prior to decoding. A command register 124 is incommunication with I/O control circuitry 112 and control logic 116 tolatch incoming commands.

Control logic 116 controls access to the array of memory cells 104 inresponse to the commands and generates status information for theexternal processor 130. The control logic 116 is in communication withrow decode circuitry 108 and column decode circuitry 110 to control therow decode circuitry 108 and column decode circuitry 110 in response tothe addresses. The control logic 116 includes a control register 126.The control logic 116 is configured to selectively operate the memorydevice 100 in a retention mode of operation in accordance with anembodiment. For some embodiments, control register 126 includes aregister (e.g., a 1-bit register) whose value (e.g., logic level) isindicative of whether the retention mode of operation is enabled ordisabled such that the control logic 116 could be configured to performthe retention mode of operation if the value of this retention mode ofoperation enable register indicates that the retention mode of operationis enabled. For some embodiments, control logic 116 could be configuredto perform a retention mode of operation in accordance with anembodiment in response to a command received from the processor 130 andwritten to the command register 124.

Control logic 116 is also in communication with a cache register 118.Cache register 118 latches data, either incoming or outgoing, asdirected by control logic 116 to temporarily store data while the arrayof memory cells 104 is busy writing or reading, respectively, otherdata. During a write operation, data is passed from the cache register118 to data register 120 for transfer to the array of memory cells 104;then new data is latched in the cache register 118 from the I/O controlcircuitry 112. During a read operation, data is passed from the cacheregister 118 to the I/O control circuitry 112 for output to the externalprocessor 130; then new data is passed from the data register 120 to thecache register 118. A status register 122 is in communication with I/Ocontrol circuitry 112 and control logic 116 to latch the statusinformation for output to the processor 130.

Status register 122 may include a ready/busy register. For example, a1-bit register could be used to indicate whether the memory device 100is busy (e.g., that the memory device 100 is performing an accessoperation) or ready (e.g., that the memory device 100 has completed, oris not performing, an access operation). Thus, reading the statusregister 122, such as by the processor 130 or the control logic 116,could be used to determine whether the memory device 100 is involved inan access operation or not, e.g., whether or not the memory device isready to initiate an access operation. Alternatively, or in addition,the control logic 116 of memory device 100 might provide a ready/busy(R/B#) signal to provide an indication to processor 130 of whether ornot the memory device 100 is involved in an access operation. Forexample, memory devices often provide a pin (e.g., a pin of control link132) that is asserted to a logic low, for example, when the device isinvolved in an access operation and is pulled up to a logic high whenthe device is again available (e.g., not involved in an accessoperation).

Memory device 100 receives control signals at control logic 116 fromprocessor 130 over a control link 132. The control signals may includeat least a chip enable CE#, a command latch enable CLE, an address latchenable ALE, and a write enable WE#. Additional control signals (notshown) may be further received or provided over control link 132depending upon the nature of the memory device 100. Memory device 100receives command signals (which represent commands), address signals(which represent addresses), and data signals (which represent data)from processor 130 over a multiplexed input/output (I/O) bus 134 andoutputs data to processor 130 over I/O bus 134.

For example, the commands are received over input/output (I/O) pins[7:0] of I/O bus 134 at I/O control circuitry 112 and are written intocommand register 124. The addresses are received over input/output (I/O)pins [7:0] of bus 134 at I/O control circuitry 112 and are written intoaddress register 114. The data are received over input/output (I/O) pins[7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bitdevice at I/O control circuitry 112 and are written into cache register118. The data are subsequently written into data register 120 forprogramming the array of memory cells 104. For another embodiment, cacheregister 118 may be omitted, and the data are written directly into dataregister 120. Data, e.g., from the array of memory cells 104 or thestatus register 122, are also output over input/output (I/O) pins [7:0]for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bitdevice.

Memory device 100 and processor 130 may receive power from a powersupply 140. Power supply 140 represents any combination of circuitry forproviding power to memory device 100 or processor 130. For example,power supply 140 might include a stand-alone power supply (e.g., abattery), a line-connected power supply (e.g., a switched-mode powersupply common in desktop computers and servers or an AC adapter commonfor portable electronic devices), or a combination of the two.

Power is typically received from the power supply 140 using two or morepotential nodes 142, such as a supply potential node (e.g., Vcc) and aground potential node (e.g., Vss). It is not uncommon for a power supply140 to provide more than two potential nodes 142. For example, a commonstandard for switched-mode power supplies, ATX (Advanced TechnologyeXtended) 2.0, provides, using a 28-pin connection, four potential nodes(or pins) at +3.3V, five potential nodes at +5V, four potential nodes at+12V, one potential node at −12V, and ten potential nodes at a groundpotential (e.g., 0V). The ATX 2.0 standard further provides a power-onpotential node for activating the foregoing potential nodes when it ispulled to ground by an external circuit, a standby potential node drivento +5V regardless of whether the other potential nodes are being drivento their respective voltages (which can be used to power the externalcircuit responsible for pulling the power-on potential node to ground),and a power-good potential node for indicating when the other potentialnodes are stabilized at their respective voltages. The remaining pin ofthe ATX 2.0 28-pin standard is undefined. Memory device 100 andprocessor 130 may utilize differing combinations of potential nodes 142from power supply 140 depending upon their respective power needs.

Processor 130 may be configured to detect whether a particular (e.g.,line-connected) power supply is available, such as where power supply140 can include more than one power supply, such as both a stand-alonepower supply and a line-connected power supply. Processor 130 might thenbe configured to operate connected apparatus, such as the memory device100, in different modes depending upon what power supplies areavailable. For example, the processor 130 might be configured to operatethe memory device 100 in a retention mode of operation in accordancewith an embodiment when a line-connected power supply is available, andmight be configured to operate the memory device 100 in a normal modewhen a line-connected power supply is not available. For example, when aline-connected power supply is available, the processor 130 mightinstruct the memory device 100 to write a value to the control register126 (e.g., by the control logic 116) to indicate that a retention modeof operation is enabled, such that the memory device 100 could performthe retention mode of operation autonomously while the retention mode ofoperation is enabled. When the line-connected power supply is no longeravailable, the processor 130 could then instruct the memory device 100to write a value to the control register 126 to indicate that theretention mode of operation is disabled. Alternatively, or in addition,the processor 130, if a line-connected power supply is available, mightsend a command to the memory device 100 to instruct the memory device100 to enter the retention mode of operation between commands to access(e.g., read, program or erase) the array of memory cells 104.

It will be appreciated by those skilled in the art that additionalcircuitry and signals can be provided, and that the electronic system ofFIG. 1 has been simplified. It should be recognized that thefunctionality of the various block components described with referenceto FIG. 1 may not necessarily be segregated to distinct components orcomponent portions of an integrated circuit device. For example, asingle component or component portion of an integrated circuit devicecould be adapted to perform the functionality of more than one blockcomponent of FIG. 1. Alternatively, one or more components or componentportions of an integrated circuit device could be combined to performthe functionality of a single block component of FIG. 1.

Additionally, while specific I/O, command and power pins are describedin accordance with popular conventions for receipt and output of thevarious signals, it is noted that other combinations or numbers of pinsmay be used in various embodiments.

FIG. 2A is a schematic of an array of memory cells 200A, e.g., as aportion of the array of memory cells 104, in accordance with anembodiment. Array of memory cells 200A includes access lines, such asword lines 202 ₀ to 202 _(N), and intersecting data lines, such as bitlines 204 ₀ to 204 _(M). For ease of addressing in the digitalenvironment, the number of word lines 202 and the number of bit lines204 are generally each some power of two, e.g., 256 word lines 202 by4,096 bit lines 204.

Array of memory cells 200A is arranged in rows (each corresponding to aword line 202) and columns (each corresponding to a bit line 204). Eachcolumn may include a string of memory cells 208, such as one of the NANDstrings 206. Each NAND string 206 may be coupled to a common source(SRC) 216 and includes memory cells 208 ₀ to 208 _(N), each located atan intersection of a word line 202 and a bit line 204. The memory cells208, depicted as floating-gate transistors in FIG. 2A, representnon-volatile memory cells for storage of data. Memory cells 208 may be,for example, enhancement mode (e.g., n-type) transistors. The memorycells 208 of each NAND string 206 are connected in series, source todrain, between a source select line (SGS) 214 and a drain select line(SGD) 215.

Source select line 214 includes a source select gate 210, e.g., afield-effect transistor (FET), at each intersection between a NANDstring 206 and source select line 214, and drain select line 215includes a drain select gate 212, e.g., a field-effect transistor (FET),at each intersection between a NAND string 206 and drain select line215. In this way, the memory cells 208 of each NAND string 206 areconnected between a source select gate 210 and a drain select gate 212.Arrays of memory cells utilizing more than one select gate at one orboth ends of a NAND string 206 are known. If multiple source selectgates 210 are utilized for a given string of memory cells 206, theycould be coupled in series between the common source 216 and the memorycell 208 ₀ of that string of memory cells 206. If multiple drain selectgates 212 are utilized for a given string of memory cells 206, theycould be coupled in series between the corresponding bit line 204 andthe memory cell 208 _(N) of that string of memory cells 206.

A source of each source select gate 210 is connected to common source216. The drain of each source select gate 210 is connected to the sourceof the memory cell 208 of a corresponding NAND string 206. Therefore,each source select gate 210 selectively couples its corresponding NANDstring 206 to common source 216. A control gate of each source selectgate 210 is connected to source select line 214.

The drain of each drain select gate 212 is connected to the bit line 204for the corresponding NAND string 206. The source of each drain selectgate 212 is connected to the drain of the last memory cell 208 _(N) ofits corresponding NAND string 206. Therefore, each drain select gate 212selectively couples a corresponding NAND string 206 to a correspondingbit line 204. A control gate of each drain select gate 212 is connectedto drain select line 215.

Typical construction of memory cells 208 includes a source 230 and adrain 232, a data-storage structure 234 (e.g., a floating gate, chargetrap, etc.) that can determines a data state of the cell (e.g., throughchanges in threshold voltage), a control gate 236, and a body 238 (e.g.,a semiconductor on which the memory cell 208 is formed), as shown inFIG. 2A. Memory cells 208 have their control gates 236 coupled to (andin some cases from) a word line 202. A column of the memory cells 208 isa NAND string 206 or a plurality of NAND strings 206 coupled to a givenbit line 204. A row of the memory cells 208 are memory cells 208commonly coupled to a given word line 202. A row of memory cells 208can, but need not include all memory cells 208 commonly coupled to agiven word line 202. Rows of memory cells 208 often include every othermemory cell 208 commonly coupled to a given word line 202. For example,memory cells 208 commonly coupled to word line 202 _(N) and selectivelycoupled to even bit lines 204 (e.g., bit lines 204 ₀, 204 ₂, 204 ₄,etc.) may be one row of memory cells 208 (e.g., even memory cells) whilememory cells 208 commonly coupled to word line 202 _(N) and selectivelycoupled to odd bit lines 204 (e.g., bit lines 204 ₁, 204 ₃, 204 ₅, etc.)may be another row of memory cells 208 (e.g., odd memory cells).Although bit lines 204 ₃-404 ₅ are not expressly depicted in FIG. 2A, itis apparent from the figure that the bit lines 204 of the array ofmemory cells 200A may be numbered consecutively from bit line 204 ₀ tobit line 204 _(M). Other groupings of memory cells 208 commonly coupledto a given word line 202 may also define a row of memory cells 208.

FIG. 2B is a schematic of an array of memory cells 200B, e.g., as aportion of the array of memory cells 104, in accordance with anotherembodiment. Array of memory cells 200B may include NAND strings 206,word lines 202, bit lines 204, source select lines 214, drain selectlines 215 and common source 216 as depicted in FIG. 2A. The array ofmemory cells 200A may be a portion of the array of memory cells 200B,for example. FIG. 2B depicts groupings of NAND strings 206 into blocks250. Blocks 250 may be erase blocks, e.g., groupings of memory cells 208that may be erased together in a single erase operation.

Although the examples of FIGS. 2A-2B were discussed in conjunction withNAND architecture memory, the embodiments described herein are notlimited to NAND architecture memory. As such, the array of memory cells104 can include other memory architectures, such as NOR architecture,AND architecture, etc.

FIG. 3 illustrates an example of Vt ranges 360 as might represent apopulation of MLC (four level) (e.g., 2-bit) memory cells for use indiscussing various embodiments. For example, a memory cell might beprogrammed to a Vt that falls within one of four different Vt ranges362-368 of 200 mV, each being used to represent a data statecorresponding to a bit pattern comprised of two bits. Typically, a deadspace (e.g., sometimes referred to as a margin, and which might have arange of 200 mV to 400 mV) is maintained between each Vt range 362-368to keep the ranges from overlapping. As an example, if the Vt of amemory cell is within the first of the four Vt ranges 362, the cell inthis case is storing a logical ‘11’ state and is typically consideredthe erased state of the cell. If the Vt is within the second of the fourVt ranges 364, the cell in this case is storing a logical ‘10’ state. AVt in the third Vt range 366 of the four Vt ranges would indicate thatthe cell in this case is storing a logical ‘00’ state. Finally, a Vtresiding in the fourth Vt range 368 indicates that a logical ‘01’ stateis stored in the cell.

Floating-gate memory cells of a particular size (e.g., having aparticular channel length and width, and a particular floating gatevolume) might have a neutral Vt (Vt₀) occurring at dashed line 370 alongthe continuum of threshold voltages. The neutral Vt represents thethreshold voltage that the memory cell might naturally assume over timeabsent external driving forces to add or remove charge from the floatinggate. As the geometries of floating-gate memory cells are reduced, theneutral Vt may tend to move lower within the continuum of thresholdvoltages. For example, floating-gate memory cells of the sameconstruction as the memory cells having the neutral Vt occurring atdashed line 370, but smaller, might have a neutral Vt occurring atdashed line 372. As the neutral Vt moves closer to either extreme of thecontinuum of threshold voltages, the pull on certain memory cells tomove toward their neutral Vt, i.e., those memory cells having datastates closer to the other extreme of the continuum of thresholdvoltages, can increase. As an example, memory cells programmed to a Vtwithin Vt range 368 might have a stronger tendency to see a shift (e.g.,a reduction) in threshold voltage over time if their neutral Vt occursat dashed line 372 rather than at dashed line 370, while memory cellsprogrammed to a Vt within Vt range 362 might have a lesser tendency tosee a shift (e.g., an increase) in threshold voltage over time if theirneutral Vt occurs at dashed line 372 rather than at dashed line 370.Various embodiments seek to mitigate this imbalance, e.g., to even outthe natural pull toward the neutral Vt such that memory cells programmedto threshold voltages at either end of the continuum of thresholdvoltages experience similar tendencies toward their neutral Vt, therebyreducing the maximum electric field across gate dielectrics of a randompopulation of memory cells. Mitigating this imbalance may facilitate animprovement in data retention of an array of memory cells.

An indicator of this tendency to shift threshold voltages might beexpressed as an electric field across a memory cell. This electric fieldmay be represented as a voltage across the gate dielectric of a memorycell (V_(ox)), and might be given by Equation 1:V _(ox)=α_(g)(−V _(G) +Vt−Vt ₀ +V _(FB))  (Eq. 1)

-   -   where:        -   α_(g) is the gate coupling ratio;        -   V_(G) is the control gate voltage;        -   Vt is the threshold voltage;        -   Vt₀ is the neutral threshold voltage; and        -   V_(FB) is the flat-band voltage (e.g., voltage of the body).

To continue with the example of FIG. 3, a first memory cell might haveits neutral Vt occurring at dashed line 370 and a second memory cellmight have its neutral Vt occurring at dashed line 372. Assume thatdashed line 370 represents a Vt₀ of +1V and dashed line 372 represents aVt₀ of −1V, that the gate coupling ratio of both the first memory celland the second memory cell are the same, e.g., 0.5, that both memorycells are receiving a control gate voltage of 0V, and that both memorycells have a flat-band voltage of 0V. In this example, the first memorycell would have a V_(ox) of +1.5V if its Vt were 4V (e.g., a memory cellprogrammed to have a threshold voltage in Vt range 368), and would havea V_(ox) of −1.5V if its Vt were −2V (e.g., a memory cell programmed tohave a threshold voltage in Vt range 362). However, the second memorycell would have a V_(ox) of +2.5V if its Vt were 4V (e.g., a memory cellprogrammed to have a threshold voltage in Vt range 368), and would havea V_(ox) of −0.5V if its Vt were −2V (e.g., a memory cell programmed tohave a threshold voltage in Vt range 362). Presuming that data retentionof an array of memory cells generally varies inversely withmax(|V_(ox)|) (a maximum absolute value of V_(ox)) for the various datastates to which a memory cell of that array might be programmed, it maybe desirable to reduce this value.

Reducing max(|V_(ox)|) for a memory cell that does not have its Vt₀occurring midway between its highest programmed threshold voltage andits lowest programmed threshold voltage can be achieved by applying anon-zero voltage differential across the memory cell, by biasing thecontrol gate, the body or both, while the memory cell is not beingaccessed. As used herein, applying a non-zero voltage differentialacross the memory cell involves actively driving a voltage differentialand does not include passive voltage differentials, such as inherentvoltage differentials due the a charge level stored by the memory cell,coupling effects that might induce a voltage differential between afloating control gate and a floating body, or voltage differentials thatmight result from a control gate and a body being coupled to a samepotential node, but equilibrating at different potential levels due todifferences in path to the potential node or the like.

In this example of a memory cell having a Vt₀ of −1 V, a highestprogrammed threshold voltage of +4V, and a lowest programmed thresholdvoltage of −2V, a theoretical minima of max(|V_(ox)|) could then beobtained by applying a control gate voltage (V_(G)) of +2V while thebody is maintained at a ground potential (e.g., 0V). It will be apparentthat similar results could be obtained by instead applying a voltage tothe body of −2V while a voltage to the control gate is maintained at theground potential, or applying a voltage to the substrate of −1V and avoltage to the control gate of +1V, etc. In addition, where a desiredV_(G) to reduce max(|V_(ox)|) in Eq. 1 is negative, a positive voltagecould be applied to the body while the control gate is biased to aground potential, for example. Thus, while examples may refer toapplying a particular V_(G), it is to be understood that equivalentapplication of voltages across the gate dielectric, either through thebody, the control gate or both, can be readily substituted to achievethe desired voltage differential to reduce max(|V_(ox)|).

FIG. 4 is a chart showing one example of a plot 474 of max(|V_(ox)|) forEquation 1, where α_(g)=0.5, Vt₀ is −1V, V_(FB) is 0V, the highestprogrammed threshold voltage is +4V, the lowest programmed thresholdvoltage is −2V, and V_(G) is varied from −4V to +6V. As depicted in FIG.4, the slope of plot 474 is negative until it reaches a theoreticalminima 475 at V_(G)=+2V, then turns positive for increasing values ofV_(G). As such, it is expected that increases in data retention could befacilitated by applying a non-zero, and in this particular example,positive voltage differential (e.g., from the control gate to the body)across the memory cells when they are not being accessed (e.g., accessedduring a read operation, erase operation or programming operation). Forthis particular example, increases in data retention might be expectedfor values of V_(G) of greater than 0V and less than +4V as the valuesof max(|V_(ox)|) for plot 474 within this range would be less than thevalue of max(|V_(ox)|) at V_(G)=0V. For certain embodiments, voltagesapplied when memory cells are not being accessed are selected to resultin a reduction of max(|V_(ox)|) of at least 20% from its value atV_(G)=0V. In the example of FIG. 4, this would represent a range ofvalues of V_(G) from +1V to +3V. For further embodiments, voltagesapplied when memory cells are not being accessed are selected to resultin values of max(|V_(ox)|) of within 20% of its theoretical minima. Inthe example of FIG. 4, this would represent a range of values of V_(G)from +1.4V to +2.6V.

Table 1 is an example of voltages that might be applied during a readoperation and a retention mode of operation for a NAND string of memorycells in accordance with an embodiment. Table 1 lists example voltageswith reference to the nodes depicted in FIG. 2A, and assumes that 202_(x) is the selected word line for the read operation.

TABLE 1 Read Retention Mode Node Operation of Operation 215 6 V 0 V orfloat 202₀ 6 V 2 V 202_(x) Vread 2 V 202_(x+1) 6 V 2 V 202_(x+2) 6 V 2 V202_(x+3) 6 V 2 V 202_(N−1) 6 V 2 V 202_(N) 6 V 2 V 214 4 V 0 V or float238 0 V 0 V

As shown in Table 1, during the read operation, the selected word line202 _(x) would receive a read voltage (Vread) insufficient to activatememory cells coupled to this word line if they have a particular datastate that the read operation is attempting to sense, and sufficient toactivate memory cells coupled to this word line if they have a lowerdata state. Remaining word lines 202 ₀-202 _(N) would receive a voltage(e.g., a pass voltage) sufficient to activate memory cells coupled tothose word lines without regard to their data states, e.g., 6V in thisexample. Source select line 214 and drain select line 215 would eachreceive a voltage sufficient to activate their corresponding selectgates, e.g., 4V and 6V, respectively, in order to couple the NAND stringof memory cells to both the common source 216 and a bit line 204. Thebody 238 of each memory cell is typically held to a ground potential,e.g., 0V.

During the retention mode of operation, each of the word lines 202 ₀-202_(N) would receive substantially the same (e.g., the same) voltage,selected in conjunction with a voltage applied to the body 238 (e.g.,0V), to apply a non-zero voltage across the memory cells coupled to theword lines 202 ₀-202 _(N) to facilitate a reduction of max(|V_(ox)|) forthe range of data states the memory cells might assume. Voltages areconsidered to be substantially the same when they are intended to be thesame voltage, such as when two different nodes are driven by the same orsimilarly configured power supply node, are coupled to the same orsimilarly configured internal voltage generator, or are otherwiseintended to be powered by the same potential node, even thoughdifferences in the characteristics of the circuit elements (e.g.,resistance differences in the circuit path, fabrication differences involtage generators, in-tolerance variations in power supply output,etc.) may lead to variations in the actual applied voltages for each ofthe nodes.

In contrast to the read operation, one or both of source select line 214and drain select line 215 might receive a voltage to deactivate theircorresponding select gates, e.g., 0V, during the retention mode ofoperation in order to isolate the NAND string of memory cells from thecommon source 216 and/or a bit line 204. While deactivation of at leastone of the select gates associated with a NAND string of memory cellswould serve to inhibit current flow through the NAND string of memorycells, such as when concurrently accessing one or more memory cells ofanother NAND string of memory cells selectively coupled to the same bitline 204, for certain embodiments, the common source 216 and the bitline 204 could be allowed to float, such as when other memory cellsselectively coupled to the common source 216 and that bit line 204 arealso not involved in an access operation. Where the common source 216and the bit line 204 are allowed to float, or are maintained at the samepotential, current flow through the NAND string of memory cells wouldnot be a concern and the source select line 214 and drain select line215 could also be allowed to float.

As noted previously, the voltages at the word lines 202 and the body 238are relative, and are selected to produce a particular voltagedifferential across the memory cell to obtain a reduction ofmax(|V_(ox)|) over that which would result if no voltage differentialwere applied across the memory cell for the range of data states thememory cells might assume. As such, the voltages of Table 1 are merelyone example.

FIG. 5 is a flowchart of a method of operating an apparatus, e.g., amemory device, in accordance with an embodiment. The method could beperformed, for example, autonomously by control logic of the memorydevice. At 576, an access operation is performed on a memory cell. Forexample, the access operation could be a read operation to determine adata state stored by the memory cell, a programming operation to write adata state to the memory cell, or an erase operation to erase the memorycell. The access operation might be initiated in response to a commandreceived from an external device, such as a processor. As discussed, theaccess operation could involve additional memory cells either directly(e.g., accessing other memory cells concurrently) or indirectly (e.g.,applying voltages to memory cells to facilitate the accessing of thememory cell or other directly involved memory cells). At 578, e.g., atthe completion of the access operation, a determination is made whethera retention mode of operation is enabled. If not, the method couldproceed to 580 where it would end. For example, control logic of thememory device may simply wait for the next command. If it is determinedthat a retention mode of operation is enabled at 578, the method couldproceed to 582 where it would enter the retention mode of operation. Forexample, in the retention mode of operation, control logic of the memorydevice could apply a non-zero voltage differential across the memorycell while waiting for the next command. For various embodiments, thatapplied voltage is selected to reduce the maximum electric field thatthe gate dielectric of the memory cell might experience if programmed toany threshold voltage along its continuum of data states. For variousembodiments, the memory device would indicate that it is available, suchas indicating the memory device is ready using a ready/busy signal orsetting a status register indicating the memory device is ready, duringthe retention mode of operation.

For some embodiments, the retention mode of operation is entered onlywhen no memory cell of an array of memory cells is involved in an accessoperation. For other embodiments, the retention mode of operation isentered for any memory cell that is not involved in an access operation,either directly or indirectly. Embodiments entering retention modes ofoperation only when no memory cell of an array of memory cells isinvolved in an access operation could simplify the control logic andutilize relatively lower power levels, while embodiments enteringretention mode of operation for any memory cell that is not involved inan access operation could facilitate higher levels of improvement indata retention characteristics, but also utilize relatively higher powerlevels.

Other embodiments might fall between these two examples, such that aretention mode of operation is entered for a subset of an array ofmemory cells when no memory cell of that subset is involved in an accessoperation. For example, with reference to FIG. 2B, word lines 202 ofblocks 250 ₀ and 250 ₁ might be multiplexed to the same global wordlines (not shown in FIG. 2B) such that applying voltages to the wordlines 202 of block 250 ₀ for an access operation on one or more memorycells of block 250 ₀ would preclude applying voltages to the word lines202 of block 250 ₁ for a retention mode of operation, even though memorycells of block 250 ₁ are not involved in an access operation. Howeverword lines 202 of blocks 250 ₂ and 250 ₃ might be multiplexed to adifferent set of global word lines (not shown in FIG. 2B) such that aretention mode of operation could be entered for memory cells of theseblocks even though one or more memory cells of blocks 250 ₀ or 250 ₁ areinvolved in an access operation as word lines 202 of blocks 250 ₂ and250 ₃ could have voltages applied for the retention mode of operationwhile word lines 202 of block 250 ₀ or 250 ₁ have voltages applied fortheir access operation.

An apparatus, e.g., a memory device, might be configured to selectivelyperform one or more of these various types of retention modes ofoperation. For example, a 2-bit register (e.g., as part of a controlregister) could indicate whether any of the foregoing three examples ofretention modes of operation are enabled or whether they are alldisabled. A user of the memory device could then select, by writing theappropriate value to the register, which retention mode of operation, ifany, the memory device should enter. The user could select the retentionmode of operation based on factors such as desired power utilization anddesired data retention characteristics. For some embodiments, theprocessor might be configured to select a type of retention mode ofoperation based on what power supplies are available.

FIG. 6 is a flowchart of a method of operating an apparatus, e.g., anelectronic system, in accordance with an embodiment. The method could beperformed by a processor in communication with a memory device, forexample. At 684, a command for an access operation is transmitted, e.g.,from a processor to a memory device. The method then waits forcompletion of the access operation at 686. Completion of the accessoperation might be indicated by a ready/busy signal of a memory device,or a processor may poll a status register of a memory device todetermine completion. At 688, it is determined whether a particular,e.g., line-connected, power supply is available. Such ability todetermine what power supplies are available is common in laptopcomputers, for example.

If the particular power supply is not available at 688, the method mightproceed to 690 to indicate that a normal mode of operation is desired.For example, if a retention mode of operation is entered by anapparatus, e.g., a memory device, in response to an external command,the method might simply do nothing, i.e., not transmit a command toplace the memory device in a retention mode of operation. For anapparatus, e.g., a memory device, utilizing a register to indicatewhether a retention mode of operation is enabled or disabled, the methodmight transmit a command to the memory device to write a value to theregister to indicate that retention modes of operation are disabled, orit might do nothing if the register currently contains that value.

If the particular power supply is available at 688, the method mightproceed to 692 to indicate that a retention mode of operation isdesired. For example, if a retention mode of operation is entered by anapparatus, e.g., a memory device, in response to an external command,the method might transmit a command to place the memory device in aretention mode of operation. Where multiple retention modes of operationare available, the command might further specify which type of retentionmode of operation is desired. For an apparatus, e.g., a memory device,utilizing a register to indicate whether a retention mode of operationis enabled or disabled, the method might transmit a command to thememory device to write a value to the register to indicate whichretention mode of operation is enabled, or it might do nothing if theregister currently contains that value.

For some embodiments, it may be desirable to continue to monitor whetherthe particular, e.g., line-connected, power supply is available. Forexample, if a line-connected power supply were no longer available, andthe apparatus switched to a battery, it might be desirable to limit thepower demands of the apparatus by discontinuing the application ofvoltages across memory cells not involved in an access operation andreverting to a normal mode of operation, i.e., where memory cells notinvolved in an access operation are not actively driven. Conversely, ifa line-connected power supply becomes available while the apparatus isin a normal mode of operation, it may be desirable to enter a retentionmode of operation to improve data retention characteristics. As such,both 690 and 692 might proceed to 694 where it is determined, e.g.,periodically or through interrupts, whether the particular power supplyis available, which would proceed to 692 if the particular power supplyis or becomes available, and would proceed to 690 if the particularpower supply is not or is no longer available.

While applying voltages across memory cells when they are not beingaccessed can be used to facilitate increases in data retention, suchoperation would generally utilize more power than normal operation.Furthermore, if a block of memory cells contained a defect, this couldlead to large, and unnecessary, current draws, such as in the case of anelectrical short defect. As such, it may be desirable to avoid applyingsuch voltages to the memory cells of defective blocks during theretention mode of operation:

FIG. 7 is a schematic of a portion of an array of memory cells showingcombinatorial logic for use with embodiments. FIG. 7 depicts a block ofmemory cells 250, such as shown in more detail in FIGS. 2A and 2B. Theblock of memory cells 250 is selectively coupled to global word lines(e.g., gwl₀-gwl_(N)) and global source select line (e.g., gsgs) andglobal drain select line (e.g., gsgd) through a multiplexer 796, only aportion of which is shown for clarity. In operation, NAND gate 797outputs a logic 0 on its output if the address of the access operationmatches the block address of block 250, and outputs a logic 1 level ifthere is no match. The output of the NAND gate 797 is provided as oneinput to NOR gate 798, and a bad block flag (BadBLK_flag) indicative ofwhether the block 250 has been deemed to be defective is provided as theother input to NOR gate 798. The bad block flag has a logic 1 level ifblock 250 is deemed defective, and a logic 0 level if it is not deemeddefective. As such, NOR gate 798 would have a logic 1 level if there wasan address match and the block was not deemed defective, and would havea logic 0 level if there was no address match or the block was deemeddefective. The output of the NOR gate 798 can be used to selectivelyactivate the level shifter 799, e.g., in response to a logic 1 level,which in turn can be used to selectively activate the transistors of themultiplexor 796 corresponding to the block 250. In this manner, even ifthe voltages for the retention mode of operation are applied to globalword lines, the word lines of the block 250 can be isolated and allowedto float if the block is deemed defective, thereby mitigating anycurrent draw.

CONCLUSION

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe embodiments will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the embodiments.

What is claimed is:
 1. A method of operating an apparatus, comprising:performing an access operation involving a memory cell of an array ofmemory cells; and applying a non-zero voltage differential across thememory cell while not involving the memory cell in any access operationon the array of memory cells.
 2. The method of claim 1, furthercomprising: selecting a value of the non-zero voltage differential inresponse to a neutral threshold voltage of memory cells of the array ofmemory cells, a gate coupling ratio of memory cells of the array ofmemory cells, and threshold voltages for data states to which theapparatus is configured to program memory cells of the array of memorycells.
 3. The method of claim 1, further comprising: determining amaximum absolute value of an electric field that would be producedacross a gate dielectric of the memory cell if the memory cell wereprogrammed to any data state to which the apparatus is configured toprogram that memory cell and if a zero voltage differential were appliedacross the memory cell; and selecting a value of the non-zero voltagedifferential to reduce the maximum absolute value of the electric fieldif the non-zero voltage differential were applied across the memorycell.
 4. The method of claim 1, wherein applying a non-zero voltagedifferential across the memory cell comprises applying a first voltageto a control gate of the memory cell and applying a second voltage to abody of the memory cell.
 5. The method of claim 4, further comprisingapplying either the first voltage or the second voltage as a groundpotential.
 6. The method of claim 1, wherein applying a non-zero voltagedifferential across the memory cell while not involving the memory cellin any access operation on the array of memory cells comprises applyingthe non-zero voltage differential across the memory cell while applyingthe non-zero voltage differential across other memory cells of the arrayof memory cells and while not involving the other memory cells in anyaccess operation on the array.
 7. The method of claim 1, furthercomprising: applying the non-zero voltage differential across the memorycell while not involving the memory cell in any access operation on thearray of memory cells only if the memory cell is not deemed defective.8. A method of operating an apparatus, comprising: applying a non-zerovoltage differential across the memory cell while a particular mode ofoperation is enabled and while not involving the memory cell in anyaccess operation on the array of memory cells; and not applying thenon-zero voltage differential across the memory cell while not involvingthe memory cell in any access operation on the array of memory cells ifthe particular mode of operation is disabled.
 9. The method of claim 8,further comprising: indicating a desire to enable the particular mode ofoperation when a particular power supply is detected as available to theapparatus; and indicating a desire to disable the particular mode ofoperation when the particular power supply is detected as not availableto the apparatus.
 10. The method of claim 8, wherein the particular modeof operation has a plurality of types, the method further comprising:applying the non-zero voltage differential across the memory cell, whilethe particular mode of operation is enabled and is of a first type,regardless of whether any other memory cells of the array of memorycells are involved in any access operation; and applying the non-zerovoltage differential across the memory cell, while the particular modeof operation is enabled and is of a second type, only while notinvolving any memory cell of a particular set of memory cells of thearray of memory cells in any access operation.
 11. The method of claim10, further comprising: applying the non-zero voltage differentialacross the memory cell, while the particular mode of operation isenabled and is of a third type, only while not involving any memory cellof the array of memory cells in any access operation; wherein theparticular set of memory cells contains less than all memory cells ofthe array of memory cells.
 12. The method of claim 10, wherein theapparatus is configured to access the memory cell using a global wordline of a particular set of global word lines, and wherein theparticular set of memory cells consists of memory cells of the array ofmemory cells for which the apparatus is configured to access using anyglobal word line of the particular set of global word lines.
 13. Themethod of claim 8, further comprising: not applying the non-zero voltagedifferential across the memory cell while not involving the memory cellin any access operation on the array of memory cells if the memory cellis deemed to be defective, regardless of whether the particular mode isenabled.
 14. The method of claim 8, wherein applying a non-zero voltagedifferential across the memory cell comprises applying the non-zerovoltage differential across an enhancement mode transistor.
 15. Themethod of claim 8, wherein applying a non-zero voltage differentialacross the memory cell comprises applying the non-zero voltagedifferential across a floating-gate transistor.
 16. A method ofoperating an apparatus, comprising: applying a non-zero voltagedifferential across a memory cell of an array of memory cells; andindicating that the apparatus is ready to initiate an access operationon the memory cell while applying the non-zero voltage differentialacross the memory cell.
 17. The method of claim 16, wherein indicatingthat the apparatus is ready to initiate an access operation comprisessetting a particular value of a register of the apparatus.
 18. Themethod of claim 16, wherein indicating that the apparatus is ready toinitiate an access operation comprises asserting a particular signallevel from the apparatus.
 19. The method of claim 16, furthercomprising: discontinuing applying the non-zero voltage differentialacross the memory cell in response to receiving a command to initiate anaccess operation.
 20. The method of claim 16, further comprising:determining a first value of an electric field that would be producedacross a gate dielectric of the memory cell if the memory cell wereprogrammed to a first data state having a highest programmed thresholdvoltage of any data state to which the apparatus is configured toprogram the memory cell and a zero voltage differential were appliedacross the memory cell; determining a second value of the electric fieldthat would be produced across the gate dielectric of the memory cell ifthe memory cell were programmed to a second data state having a lowestprogrammed threshold voltage of any data state to which the apparatus isconfigured to program the memory cell and a zero voltage differentialwere applied across the memory cell; and selecting a value of thenon-zero voltage differential such that absolute values of the electricfields that would be produced across the gate dielectric of the memorycell while applying the non-zero voltage differential across the memorycell if the memory cell were programmed to either the first data stateor the second data state are both less than a maximum absolute value ofthe first value and the second value.